1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device, and in particular, to the structure of bit line contacts in a memory cell array of a nonvolatile semiconductor memory device and a method for manufacturing the nonvolatile semiconductor memory device. The present invention is used in, for example, NOR type flash memories.
2. Description of the Related Art
A NOR type flash memory has a large number of memory cells each including a nonvolatile transistor having a 2-layer gate structure. The large number of memory cells constitute a memory cell array. A well region is formed in a front layer portion of a silicon substrate. Active regions of the large number of memory cell transistors are arranged in a matrix within the well region. Each of the activate regions includes a source region, a drain region, and a channel region. Two memory transistors adjacent to each other in a column direction share the drain region. Shallow trench isolations (STI) are each formed between rows of memory transistors. The active regions are isolated from one another by STIs. To ensure an insulating distance between the control gate and channel region of the memory cell transistor, the top surface of the active region, which constitutes the channel region, is formed lower than the top surface of a filling oxide film in STI. The top surfaces of the filling materials in STIs each present between columns of memory cell transistors have a uniform height.
Jpn. Pat. Appln. KOKAI Publication No. 2005-79282 discloses a nonvolatile semiconductor memory device in which the top surfaces of the filling materials in STIs have a uniform height. When the top surfaces of the filling materials in STIs have a uniform height, the top surface of the drain region is lower than that of the filling oxide film of STI adjacent to the drain region. This makes it difficult to form a drain contact electrically connected to the drain region, increasing a variation in contact resistance. As a result, the memory cells may operate improperly or their characteristics may be degraded.